In many types of digital logic circuitry it is often desirable to sense a transition in a particular signal and generate a latched output signal representative of such transition for as long as such output signal is required. The signal whose transition or "edge" is detected may be any variety of signal present within the digital logic circuitry, and the corresponding latched signal may be used for any number of purposes. Generally, the latched signal remains in the state representative of the detected condition until such time as it is no longer required, irrespective of further transitions in the detected signal. The latched signal may be reset to its original state by application of a reset signal to appropriate reset circuitry. To eliminate the detection of undesired transitions in the detected signal, the edge sense latch may be controlled by a control or clock signal, so that only those transitions occurring during a predetermined level of such control or clock signal are detected and latched.
A known prior art edge sense latch comprises a pair of cross-coupled NOR gates. One of such NOR gates receives as an input thereto the output of a third NOR gate. One input to the third NOR gate receives a signal whose transition is to be detected, and the other input of the third NOR gate receives the output of a signal delaying means, such as a sequence of series-connected inverters, which delay means is itself responsive to the signal whose transition is to be detected. The prior art edge sense latch requires a relatively large number of MOS components to implement and thus consumes a relatively large amount of silicon area.
As large and medium scale MOS devices become increasingly dense and complex, the provision of simplified, yet efficient MOS logic elements becomes mandatory. The present invention meets the demand for a small, effective edge sense latch by utilizing a minimum of MOS components and by making use of the inherent capacitance existing between the physical layers of an MOS device. By utilizing the present invention in medium and large scale MOS devices requiring edge sensing and latching circuitry, the size and complexity of such devices can be considerably reduced, resulting in the production of more cost competitive and error-free devices. Moreover, by requiring fewer MOS components, the power requirements of MOS devices utilizing the present invention are reduced.